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| LCX021AM 4.1cm (1.6-inch) LCD Panel (with microlens) For the availability of this product, please contact the sales office. Description The LCX021AM is a 4.1cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel allows full-color representation without color filters through the use of a microlens. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines. The adoption of an advanced on-chip black matrix realizes high picture quality by incorporating a high luminance screen, cross-talk free and ghost free circuits. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals. The panel contains an active area variable circuit which supports SVGA 4:3/PC981 8:5 data signals by changing the active area according to the type of input signal. 1 "PC98" is a trademark of NEC Corporation. Features * The number of active dots: 1,456,000 (1.6-inch; 4.1cm in diagonal) * Supports SVGA (804 x 3 x 604) and PC981 (804 x 3 x 500) * Effective aperture ratio: 70% (reference value) * Built-in cross talk free and ghost free circuits * High contrast ratio with normally white mode: 150 (typ.) * Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) * Up/down and/or right/left inverse display function Element Structure * Dots: 804 x 3 (H) x 604 (V) = 1,456,848 * Built-in peripheral driver using polycrystalline silicon super thin film transistors Applications * Liquid crystal data projectors * Liquid crystal projectors * Liquid crystal rear projection TV, etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98501A94-PS V Shift Register (Bidirectional Scanning) Black Frame Control Circuit Precharge Control Circuit Black Frame Control Circuit V Shift Register (Bidirectional Scanning) -2- Block Diagram 3 4 5 PSIGB PSIGG PSIGR Up/Down and/or Right/Left Inversion Control Circuit RGT DWN HST HCK1 HCK2 BLK ENB VCK VST PCG MODE 25 34 26 27 Input Signal Level Shifter Circuit H Shift Register (Bidirectional Scanning) 28 30 31 32 33 35 36 24 37 29 38 6 7 8 HVDD VVDD VSS TEST SIGB1 SIGB2 SIGB3 SIGB4 SIGB5 SIGB6 SIGG1 SIGG2 SIGG3 SIGG4 SIGG5 SIGG6 SIGR1 SIGR2 SIGR3 SIGR4 SIGR5 SIGR6 COM 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 39 COM PAD LCX021AM LCX021AM Absolute Maximum Ratings (VSS = 0V) * H driver supply voltage HVDD * V driver supply voltage VVDD * Common pad voltage COM * H shift register input pin voltage HST, HCK1, HCK2, RGT * V shift register input pin voltage VST, VCK, PCG, BLK, ENB, DWN, MODE * Video signal input pin voltage SIGB1, SIGB2, SIGB3, SIGB4, SIGB5, SIGB6, SIGG1, SIGG2, SIGG3, SIGG4, SIGG5, SIGG6, SIGR1, SIGR2, SIGR3, SIGR4, SIGR5, SIGR6, PSIGB, PSIGG, PSIGR * Operating temperature Topr * Storage temperature Tstg Operating Conditions (VSS = 0V) -1.0 to +20 -1.0 to +20 -1.0 to +17 -1.0 to +17 -1.0 to +17 -1.0 to +15 V V V V V V -10 to +70 -30 to +85 C C * Supply voltage HVDD 15.5 0.5V VVDD 15.5 0.5V * Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 0.5V -3- LCX021AM Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol NC NC PSIGB PSIGG PSIGR SIGB1 SIGB2 SIGB3 SIGB4 SIGB5 SIGB6 SIGG1 SIGG2 SIGG3 SIGG4 SIGG5 SIGG6 SIGR1 SIGR2 SIGR3 Description Leave this pin open. Leave this pin open. Blue uniformity improvement signal Green uniformity improvement signal Red uniformity improvement signal Video signal B1 to panel Video signal B2 to panel Video signal B3 to panel Video signal B4 to panel Video signal B5 to panel Video signal B6 to panel Video signal G1 to panel Video signal G2 to panel Video signal G3 to panel Video signal G4 to panel Video signal G5 to panel Video signal G6 to panel Video signal R1 to panel Video signal R2 to panel Video signal R3 to panel Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SIGR4 SIGR5 SIGR6 HVDD RGT HST HCK1 HCK2 VSS BLK ENB VCK VST DWN PCG MODE VVDD TEST COM NC Description Video signal R4 to panel Video signal R5 to panel Video signal R6 to panel Power supply for H driver Drive direction pulse for V shift register (H: normal, L: reverse) Start pulse for H shift register drive Clock pulse 1 for H shift register drive Clock pulse 2 for H shift register drive GND (H, V drivers) Black frame display pulse Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Improvement pulse for uniformity Display area switching (H: SVGA, L: PC98) Power supply for V driver Test; Open Common voltage of panel Leave this pin open. Note) RGB video signals of Pins 6 to 23 is an example. The order of RGB can be changed. -4- LCX021AM Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except video signal inputs. All pins are connected to VSS with a high resistor of 1M (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) SIGB1, SIGB2, SIGB3, SIGB4, SIGB5, SIGB6, SIGG1, SIGG2, SIGG3, SIGG4, SIGG5, SIGG6, SIGR1, SIGR2, SIGR3, SIGR4, SIGR5, SIGR6, PSIGB, PSIGG, PSIGR HVDD Input 1M Signal line (2) HCK1, HCK2 HVDD 250 250 Level conversion circuit (2-phase input) 1M 250 1M Input 250 (3) RGT Input HVDD 2.5k 2.5k Level conversion circuit (single-phase input) 1M (4) HST Input HVDD 250 250 Level conversion circuit (single-phase input) 1M (5) PCG, VCK VVDD 250 Input 1M 250 Level conversion circuit (single-phase input) (6) VST, BLK, ENB, DWN, MODE VVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input) (7) COM Input VVDD 1M LC -5- LCX021AM Input Signals 1. Input signal voltage conditions (Vss = 0V) Item H shift register input voltage (Low) HST, HCK1, HCK2, RGT (High) V shift register input voltage (Low) MODE, BLK, VST, VCK, (High) PCG, ENB, DWN Video signal center voltage Video signal input range1 Common voltage of panel2 Uniformity improvement signal input voltage (PSIGB, PSIGG, PSIGR)3 Symbol VHIL VHIH VVIL VVIH VVC Vsig Vcom Vpsig Min. -0.5 4.5 -0.5 4.5 6.8 VVC - 4.5 VVC - 0.5 VVC 4.3 Typ. 0.0 5.0 0.0 5.0 7.0 7.0 VVC - 0.4 VVC 4.5 Max. 0.4 5.5 0.4 5.5 7.2 VVC + 4.5 VVC - 0.3 VVC 4.7 Unit V V V V V V V V 1 Video input signal shall be symmetrical to VVC. 2 The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. 3 Input a uniformity improvement signals PSIGB, PSIGG and PSIGR in the same polarity with video signals SIGB1 to 6, SIGG1 to 6 and SIGR1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIGB, PSIGG and PSIGR are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below). PSIGB, PSIGG and PSIGR may change its suitable input voltage according to the drive conditions. Uniformity Improvement Signals PSIGB, PSIGG and PSIGR Input Waveform 90% PSIGB, G, R VVC 10% trPSIG tfPSIG PCG Level Conversion Circuit The LCX021AM has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 0.5V. -6- LCX021AM 2. Clock timing conditions (Ta = 25C) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn rise time4 HCK Hckn fall time4 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time Enb rise time Enb fall time ENB Vck rise/fall to Enb rise time Horizontal video period completed to Enb fall time Enb fall to Pcg rise time Pcg rise time PCG Pcg fall time Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time BLK Blk fall time Blk fall to Vst rise time Blk pulse width 4 Hckn means Hck1 and Hck2. (SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb toEnb tdEnb toPcg trPcg tfPcg toVck twPcg trBlk tfBlk toVst twBlk Min. -- -- 50 50 -- -- -15 -15 -- -- 5 5 -- -- -- -- 400 900 630 -- -- 0 1100 -- -- 1 1 Typ. -- -- 60 60 -- -- 0 0 -- -- 10 10 -- -- -- -- 500 1000 700 -- -- 1000 1200 -- -- -- -- Max. 30 30 70 70 30 30 15 15 100 100 15 15 100 100 100 100 -- -- -- 30 30 1100 1300 100 100 2 -- line ns s ns Unit -7- LCX021AM Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions * Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst 5 Hst data set-up time tdHst 50% 50% Hst Hck1 Hst data hold time thHst tdHst 50% 50% thHst 90% 10% * Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn rise time3 Hckn fall time3 HCK Hck1 fall to Hck2 rise time trHckn 90% 3 Hckn 10% tfHckn 5 to1Hck Hck1 * Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns trHckn tfHckn 50% 50% 50% Hck2 50% Hck1 rise to Hck2 fall time to2Hck to2Hck to1Hck 5 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means -. The black dot at an arrow ( ) indicates the start of measurement. -8- LCX021AM Vst 10% trVst Waveform 90% 90% 10% tfVst Conditions tfVst 5 Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst 90% Vck 10% thVst 90% 10% Vck rise time VCK Vck fall time trVck tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time tfEnb tfEn trEn ENB Vck rise/fall to Enb rise time Horizontal video period Horizontal blanking period toEnb Vck 50% Enb 50% tdEnb 50% Enb pulse width twEnb 5 Pcg toEnb toPcg Pcg rise time Pcg fall time PCG6 Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time Blk fall time BLK Blk fall to Vst rise time Blk pulse width trPcg Vck 50% toVck tfPcg toVck trPcg twBlk tfBlk toVst twBlk Blk 50% 50% twBlk toVst Pcg 50% 50% twPcg 5 Vst 50% 5 6 Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin. -9- LCX021AM Electrical Characteristics (Ta = 25C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. -- -- -500 Typ. 12 12 -250 Max. 17 17 -- -- -- -- 170 20.0 Unit pF pF A A A A pF mA HCKn: HCK1, HCK2 (4.0MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Conditions -1000 -300 -500 -150 -- -- -150 -30 120 15.0 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK Symbol CVck CVst Min. -- -- Typ. 12 12 Max. 17 17 -- -- 6.0 Unit pF pF A A mA VCK = GND PCG, VST, ENB, DWN, BLK, MODE = GND VCK: (24.0kHz) Conditions -1000 -150 -150 IV -- -30 3.0 PCG, VST, ENB, DWN, BLK, MODE Current consumption 3. Total power consumption of the panel Item Total power consumption of the panel (SVGA) Symbol Min. PWR -- Typ. 250 Max. 400 Unit mW 4. Pin input resistance Item Pin - VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. -- Unit M 5. Uniformity improvement signal Item Symbol Min. -- Typ. 10 Max. 15 Unit nF Input pin capacitance for uniformity CPSIGo improvement signal - 10 - LCX021AM Electro-optical Characteristics Item Contrast ratio Effective apeature ratio 25C 25C Symbol Measurement method Min. CR Teff RV90-25 25C V90 60C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25C V-T characteristics V50 60C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25C V10 60C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0C 25C 0C 25C 60C 25C 25C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 1 2 100 -- 1.3 1.4 1.5 1.3 1.3 1.4 1.7 1.8 1.9 1.7 1.7 1.8 2.3 2.4 2.5 2.3 2.3 2.3 -- -- -- -- -- -- -- Typ. 150 70 1.6 1.8 1.9 1.6 1.7 1.8 2.0 2.1 2.2 1.9 2.0 2.1 2.6 2.7 2.8 2.5 2.6 2.7 30 12 100 30 -65 -- -- (SVGA mode) Max. -- -- 2.0 2.2 2.3 1.9 2.0 2.2 2.3 2.4 2.5 2.2 2.3 2.4 2.9 3.0 3.1 2.8 2.9 3.0 80 40 200 70 -40 -- 5 dB s % ms V Unit -- % Reflection Preventive Processing When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection. - 11 - LCX021AM 100W lamp angle distribution 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.0 Projection lenses Relative light intensity Screen 1.0 2.0 3.0 3.5 4.0 Panel incident light dispersion angle [ ] * Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast ratio Contrast Ratio (CR) is given by the following formula (1). L (White) CR = L (Black) ... (1) L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V L (Black): Surface luminance of the panel at VAC = 4.5V Both luminosities are measured by System I. - 12 - LCX021AM 2. Effective aperture ratio Measure the luminances below on the screen in System I, and calculate the effective aperture ratio using the following formula (2). Luminance for panel with microlens Luminance for panel without microlens x (TFT aperture ratio) x 100 [%] ... (2) 3. V-T characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. The angles of incidence for R, G and B are as shown in the diagram below. Red: Center: Vertical Green: Left: 6.0 0.5 Blue: Right: 6.0 0.5 Transmittance [%] 90 50 10 V90 V50 V10 VAC - Signal amplitude [V] Left Center Right Optimum angle of incidence 6.0 0.5 Optimum angle of incidence 6.0 0.5 Pad 4. Response time Response time ton and toff are defined by formulas (3) and (4) respectively. ton = t1 - tON ...(3) toff = t2 - tOFF ...(4) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 4.5V 7.0V Input signal voltage (Waveform applied to the measured pixels) 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff - 13 - LCX021AM 5. Flicker Flicker (F) is given by the formula (5). DC and AC (SVGA:30Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in system II. F [dB] = 20log { AC component } ...(5) DC component Each input signal voltage for gray raster mode is given by Vsig = 7.0 V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 6. Image retention time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct. Monoscope signal conditions: Vsig = 7.0 4.5 or 2.0 [V] (shown in the right figure) Vcom = 6.6V Black level 4.5V 2.0V 7.0V 2.0V 4.5V White level 0V Vsig waveform 7. Cross talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 4.5V/1V). Cross talk value CTK = Wi' - Wi x 100 [%] Wi W4 W4' W2 W2' W1 W1' W3 W3' - 14 - LCX021AM Viewing Angle Characteristics (Typical Value) 90 Phi 0 180 10 30 50 70 Theta 270 0 Z 90 Marking Y 180 0 X 270 Measurement method - 15 - 1. Dot arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW B1 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 18 dots 2448 dots 2412 dots (effective 32.56mm) 18 dots Note) This RGB pixel arrangement agree with the items mentioned in the Pin Description. This RGB arrangement can be changed according to input signals. 1 dot B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 R4 604 dots (effective 24.46mm) B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 R4 B5 G5 R5 606 dots - 16 - R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B6 G6 R6 R4 B5 G5 R5 R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 R6 B6 G6 R6 G5 Active area G6 B5 R6 R4 B5 G5 R5 G5 R5 B6 G6 R6 R4 B5 G5 R5 R5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 B1 G1 R1 B2 G2 B2 R3 G3 R3 area Photo-shielding B4 G4 R4 B5 G5 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 1 dot R2 B3 G3 R3 B4 G4 R4 B5 G5 R5 B6 G6 R6 B1 G1 R1 B2 G2 R2 B3 G3 R3 B4 G4 R4 B5 G5 LCX021AM LCX021AM 2. LCD panel operations [Description of basic operations] * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 604 gate lines sequentially in a single horizontal scanning period (in SVGA mode). * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 804 x 3 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. * Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 604 x 804 x 3 dots to display a picture in a single vertical scanning period. * The data and video signals shall be input with the 1H-inverted system. [Description of operating mode] This LCD panel can change the active area by displaying a black frame to support various computer or video signals. The active area is switched by MODE. However, the center of the screen is not changed. The active area setting modes are shown below. MODE H L Display mode SVGA 804 x 3 x 604 PC98 804 x 3 x 500 This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. * Right/left inverse mode * Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below: RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside. To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the H and V systems must be varied. The phase relationship between the start pulse and the clock for each mode is shown on the following pages. - 17 - LCX021AM (1) Vertical direction display cycle (1.1) SVGA VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 601 602 603 604 Vertical display cycle 604H (1.2) PC98 VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 497 498 499 500 Vertical display cycle 500H (2) Horizontal direction display cycle (2.1) SVGA/PC98, RGT = H HD HST HCK1 HCK2 1 2 3 4 130 131 132 133 134 Horizontal display cycle (2.2) SVGA/PC98, RGT = L HD HST HCK1 HCK2 1 2 3 4 130 131 132 133 134 Horizontal display cycle - 18 - LCX021AM 3. 18-dot simultaneous sampling The horizontal shift register samples SIGB1 to SIGB6, SUGG1 to SIGG6 and SIGR1 to SIGR6 signals simultaneously. This requires phase matching between signals SIGB1 to SIGB6, SIGG1 to SIGG6 and SIGR1 to SIGR6 to prevent the horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel. The block diagram of the delaying procedure using simple-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low level), the phase settings for signals SIGB1 to SIGB6, SIGG1 to SIGG6 and SIGR1 to SIGR6 are exactly reversed. SIGB1, SIGG1, SIGR1 SIGB2, SIGG2, SIGR2 S/H CK1 S/H CK2 S/H S/H SIGB1, SIGG1, SIGR1 SIGB2, SIGG2, SIGR2 SIGB3, SIGG3, SIGR3 SIGB4, SIGG4, SIGR4 S/H CK3 S/H CK4 S/H S/H SIGB3, SIGG3, SIGR3 SIGB4, SIGG4, SIGR4 SIGB5, SIGG5, SIGR5 SIGB6, SIGG6, SIGR6 S/H CK5 S/H S/H CK6 SIGB5, SIGG5, SIGR5 SIGB6, SIGG6, SIGR6 HCKn CK1 CK2 CK3 CK4 CK5 CK6 - 19 - LCX021AM LCX021AM Display System Block Diagram An example of display system is shown below. R CXA2112R R G B CXA2111R G CXA2112R LCX021AM B CXA2112R HSYNC PLL MCK FRP CXD2464R VSYNC TIMING PULSE - 20 - LCX021AM Optical Characteristics 1. Microlens outline The LCX021AM has a single built-in microlens on the substrate side facing the TFT for the three TFT panel picture elements. This microlens serves the following purposes. (1) The microlens converges the incident light striking the LCD panel to the dot aperture in order to improve the effective aperture ratio and increase the display brightness. (2) The microlens provides a color representation by distributing the light flux for each of the three primary colors R, G and B which strike the panel at different angles to the dot apertures corresponding to each color. This allows the light utilization efficiency to be improved by eliminating the light absorption by the color filter, which had been unavoidable with conventional single panel projectors. 2. Recommended lighting conditions In order to bring out the full light converging effects of the microlens and provide a color representation with high color purity, the following lighting is recommended. (1) The incident light angle of the three primary colors should be as shown in the figure below. The center light should strike the panel from the panel normal direction, and the left and right light from angles inclined to the right and left of the panel normal direction. The design optimal angle of incidence is the range of 6.0 0.5. However, the optimal angle of incidence may be altered slightly depending on the panel. Be sure to allow adjustment of the mutual angles of the dichroic mirrors so that the angle of incidence can be varied within the range of 6.0 0.5. Left Center Right Optimum angle of incidence 6.0 0.5 Optimum angle of incidence 6.0 0.5 Pad (2) Effective light: The normal direction (center light), left light and right light noted above should strike the panel at an angle of 3.5 or less. Light with a dispersion angle greater than this value will strike adjoining dot apertures and cause the color purity to worsen. (See the incident angle distribution for System .) 3. Recommended projection optical system The maximum egress light angle for light passing through the LCD is approximately 17. Therefore, setting the F stop of the projection lens to about 1.7 is recommended in order to maximize the light converging effects of the microlens and provide a representation with excellent color balance. If the projection lens F stop is larger than this value, the right and left light are kicked accordingly by the projection lens, thereby reducing the egress light flux to the screen and the same time shifting the white balance. - 21 - LCX021AM Notes on Operation (1) Lighting spectrum and intensity Use only visible light with a wavelength = 415 to 780nm as a light source. Light with a wavelength > 780nm (infrared light) will produce unwanted temperature rises. Light with a wavelength < 415nm (ultraviolet light) will produce irreversible changes in the display characteristics. To prevent this, be sure to mount UV/IR cut filters between the LCX021AM and the light source as necessary depending on the light source. The lighting intensity should be 1 million lx or less, and the panel surface temperature should not exceed 55C. (2) Lighting optical system Care should be taken for the following points concerning the optical system mounted on the LCX021AM. 1) Light reflected from the optical system to the panel should be 20,000 lx or less. 2) Particular care should be taken for the panel incident angle distribution when designing optical systems for use with the LCX021AM. 3) The panel surface temperature distribution should not exceed 10C. 4) Light should shine only on the effective display area within the LCD panel and not on other unnecessary locations. Leakage light may produce unwanted temperature rises. - 22 - LCX021AM Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, a surface of a panel (glass panel) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the glass panel. c) Do not touch the surface of the glass panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow off dust at the glass panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 3kg * cm or less. i) Use appropriate filter to protect a panel. j) Do not pressure the portion other than mounting hole (cover). - 23 - LCX021AM Package Outline Unit: mm (5.1) Thickness of the connector 0.3 0.05 1 2 3 3 50.9 0.7 4R 1. 0 4 5 6 32.0 0.2 46.5 0.2 (24.46) 6 Polarizing Axis (1.0) Active Area Incident light 7 13.23 0.25 P 8.0 x 4 = 2.5H9 2.5H9 x 3.0 8-2.5 0.1 (28.5) 3.0 0.2 5.1 0.2 9.2 0.2 9.7 0.4 (32.56) 57.0 0.2 62.0 0.2 12.22 0.25 2.5 0.2 5.5 0.2 51.0 0.2 No P 0.5 x 39 = 19.5 0.1 0.5 0.1 + 0.04 0.35 - 0.03 Description FPC Reinforcing board Molding material Reinforcing material Outside frame Glass Polarizing film weight 48g 0.5 0.15 4.0 0.4 1 2 3 4 5 6 PIN1 PIN40 electrode (enlarged) The rotation angle of the active area relative to H and V is 1. 7 - 24 - |
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